True random number generators (TRNGs) play a critical role in information security. While the Galois ring oscillator-based TRNG (GARO-TRNG) represents a classical design architecture, it typically suffers from issues of fixed points or periodic oscillations. To address these limitations, this paper proposes a novel FPGA-based DMRO-TRNG structure with multiple entropy sources incorporating clock jitter, metastability, and chaos. Distinct from conventional GARO architectures, this dynamic TRNG design implements mode switching through MUX, enabling transitions between different operational modes to generate random output sequences. The implementation utilizes Xilinx compiler for automatic place-and-route, effectively enhancing comprehensive performance in random number generation. Experimental evaluations on Xilinx Kintex-7 and Artix-7 FPGAs demonstrate that the generated random sequences successfully pass rigorous standard tests including NIST SP800-22, NIST SP800-90B, and TESTU01. The architecture exhibits exceptional robustness under varying voltage and temperature conditions through extensive testing. With low hardware overhead, this TRNG achieves a throughput of 750 Mbps while consuming only 36 LUTs, 4 DFFs, and 16 MUXs, requiring merely a simple XOR-based post-processing circuit.