Design of loadbalancing AVOQ router in networkonchip
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1. School of Computer and Information, HefeiUniversity of Technology, Hefei 230009, China;2. School of Electronic Science and Applied Physics,HefeiUniversity of Technology, Hefei 230009, China

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TP302; TN915.03

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    Abstract:

    When congestion occurs in the network, VOQ routers still suffer a certain degree of headofline blocking (HoL) problem in the networkonchip (NoC).Aiming at this issue, we propose the loadbalancing AVOQ router architecture. Firstly, the VOQ mechanism is kept to deal with the HoL problem. Secondly, a flexible output port can be picked up in the routing computing module, making sure that the dada is ported out to the less congested road and a single virtual channel (VC) can read the packet adaptively, so that the less congested flow in the downstream can be transmitted. The experimental results show that, compared to the VC router and the VOQ router, AVOQ router reduces the average latency by 83.2% and 57.1% and improves the throughput by 72.7% and 33.3% at most, while the area overhead and power consumption are affordable. By the use of above adaptive mechanism, the network load is balanced and the congestion is relieved, and the appearing of the HoL is decreased. Moreover, the impact of HoL is eliminated as long as it appears,and the network performance is improved greatly.

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  • Received:
  • Revised:
  • Adopted:
  • Online: July 20,2017
  • Published: