True random number generators have broad application prospects in the fields of hardware and information security. In order to improve the throughput and reduce the hardware overhead of true random number generator, an autonomous Boolean network is constructed with coupled basic logic units as the entropy source. A first-order high-frequency oscillation loop is used to enhance the network refresh frequency and multi-level nonlinear amplification, thereby obtaining a high entropy chaotic signal. Combining a postprocessing circuit composed of DFF and XOR, a true random number generator is designed and implemented on an FPGA platform. The sampled output data is extracted using the ChipScope online tool, then NIST SP800-22 and SP800-90B randomness tests are performed on the data, and their performance such as offset, autocorrelation, and maximum Lyapunov exponent are evaluated. The results show that the proposed true random number generator can generate a random number sequence with an entropy value of 0. 994 847 bit / sample at a throughput rate of 600 Mbit / s, and is of low offset and no autocorrelation, and low hardware overhead.