Low voltage operational amplifiers and their digitally assisted calibration algorithms are critical in the design of ultra-high speed, high resolution analog-to-digital converters (ADCs). A 500 MS / s, 12-bit pipeline ADC based on a 40 nm CMOS process and operating voltage of 1. 1 V has been proposed. This ADC adopts a sample-and-hold (SHA) less front-end structure and low-voltage interstage operational amplifiers (opamp) to reduce power consumption. A foreground calibration algorithm using digital detection is designed for gain error and capacitance mismatch calibration, effectively improving the overall performance of the ADC using smaller area and power consumption. This digital calibration scheme improves the differential nonlinearity (DNL) and integral nonlinearity (INL) of the ADC from 2. 4 LSB and 5. 9 LSB to 1. 7 LSB and 0. 8 LSB. for a 74. 83 MHz sinusoidal signal, the calibration technique achieves a signal-to-distortion noise ratio (SNDR) of 63. 14 dB and a spurious-free dynamic range ( SFDR) of 75. 14 dB, respectively, with a power consumption of 123 mW, which meets the design targets and demonstrates the effectiveness of a low-voltage pipeline ADC design with digital correction.