Aiming at the problem of high-order amplitude phase shift keying ( APSK) demapping complexity and difficult hardware implementation, a low-complexity APSK demapping scheme and circuit implementation architecture are proposed. Specifically, the constellation map is divided into regions based on the analysis of symmetry. Then, based on the Max-Log-MAP algorithm, the bit soft information of the received symbols falling into each region is calculated and simplified, thereby obtaining a formula with a low calculation amount for calculating the soft information. Furthermore, using the characteristics of the simplified soft information calculation formula for each bit, the soft information calculation circuit architecture is designed and its performance is tested on the field programmable gate array (FPGA) hardware platform. Test results show that the APSK demapping circuit using the proposed simplified method can achieve a bit error rate (BER) of 10 -5 when the signal-to-noise ratio (SNR) is 14 dB, which is close to the performance of the traditional demapping algorithm and has lower hardware resource consumption.