| 苗其军,赵瑞康,王素珍,邹开元.大尺寸 TFT 屏视频信号的尺度变换与降场频实现[J].电子测量与仪器学报,2023,37(10):53-64 |
| 大尺寸 TFT 屏视频信号的尺度变换与降场频实现 |
| Implementation of video scaling and field frequency changing system for large-screen TFT |
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| DOI： |
| 中文关键词: 超高清、高清视频信号 尺度下变换 场频 DDR3 存储芯片 异步 FIFO 寄存器 FPGA 器件 |
| 英文关键词:ultra-high-definition and high-definition video signal down scale transformation field frequency DDR3 memory chip asynchronous FIFO register FPGA device |
| 基金项目:山东省自然科学基金(ZR2020MF003)、山东校企联合基金(RH1900012993)项目资助 |
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| 中文摘要: |
| 为解决测试超高清视频处理主板需要更换不同规格 TFT 屏幕的难题,同时进一步缩短测试耗时;提出了一种 FPGA 器
件联合 DDR3 SDRAM 存储芯片的尺度变换和降场频的系统结构,将不同分辨率和不同场频的视频信号归一化为高清视频信
号。 系统以 4 K@ 60 Hz 超高清视频作为输入信号,送到由 FPGA 控制的 DDR3 组成的视频数据读写模块中,实现数据跨时钟域
传输和尺度下变换处理及视频数据的连接;连续输出尺度下变换与降场频处理后的高清视频信号。 经对比实验测试,相较于多
路 FIFO 加 DDR3 的存储结构,消耗的存储资源减少 352 256 bit,同时转换过程耗时减少 6. 761 μs。 结果表明本系统更适用于生
产线上视频处理主板的测试需求。 |
| 英文摘要: |
| In order to solve the problem of replacing TFT screens of different specifications when testing UHD video processing
motherboards, and further shorten the test time, a system structure is proposed that combines the scale conversion and field frequency
reduction of FPGA devices with DDR3 SDRAM memory chips to normalize video signals with different resolutions and field frequencies
into HD video signals. The system uses 4 K@ 60 Hz UHD video as the input signal and sends it to the video data reading and writing
module composed of DDR3 controlled by FPGA to realize cross-domain transmission, down-scale conversion processing and data
connection; continuous output the HD video signal after down-scale conversion and field frequency reduction. After comparative
experiments, compared with the storage structure of multi-channel FIFO plus DDR3, the storage resources consumed are reduced by
352 256 bits, and the conversion process time is reduced by 6. 761 μs. The results show that this system is more suitable for the testing
requirements of video processing mainboards on production lines. |
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