电子测量与仪器学报

汪玉传,梁华国,鲁迎春,肖远.基于 STR 的两级差分的高精度低功耗 TDC[J].电子测量与仪器学报,2023,37(6):136-146

基于 STR 的两级差分的高精度低功耗 TDC

STR-based two-stage differential high-precision and low-power TDC

DOI：

中文关键词: 差分延迟链游标自定时环(STR) FPGA 边沿检测时间数字转换器(TDC)

英文关键词:differential delay chain vernier self-timing ring (STR) FPGA edge detection time to digital convert (TDC)

基金项目:国家自然科学基金重大科研仪器研制项目(62027815)、国家自然科学基金重点项目(61834006)、国家自然科学基金(62174048)项目资助

作者	单位
汪玉传	1.合肥工业大学微电子学院
梁华国	1.合肥工业大学微电子学院
鲁迎春	1.合肥工业大学微电子学院
肖远	1.合肥工业大学微电子学院

Author	Institution
Wang Yuchuan	1.School of Microelectronics,Hefei University of Technology
Liang Huaguo	1.School of Microelectronics,Hefei University of Technology
Lu Yingchun	1.School of Microelectronics,Hefei University of Technology
Xiao Yuan	1.School of Microelectronics,Hefei University of Technology

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中文摘要:

随着集成电路工艺的发展和集成度的提高,电路延时显著降低,传统的时间数字转换器(TDC)的研究趋向于兼具高分辨率和高精度的电路设计。近年来,摩尔定律逐渐失效,物联网大背景下轻量化,微型化,低功耗的边缘设备得到了飞速发展, 用于片上延时测量的微型化 TDC 的研究重点逐步转向高精度的低功耗设计。基于 Xilinx Virtex-6 XC6VLX240T 现场可编程门阵列( FPGA)开发平台,提出了一种以游标自定时环(vernier self timing ring, VSTR)代替直接计数法的粗测结构,和两条对称的延迟链组成的细测结构。通过边沿重合检测单元和锁存单元将粗测结构的游标 STR 与细测的对称延迟链结合,设计结果表明该结构量程可达到 491 ns,分辨率为 14. 8 ps,最高精度为 12. 9 ps,功耗为 0. 068 W,说明了提出的两级差分结构具有高精度低功耗的特点。

英文摘要:

With the development of integrated circuit technology and increased integration, circuit delay has significantly decreased. The research on traditional time-to-digital converters (TDC) tends to focus on circuit designs that combine high resolution and high accuracy. In recent years, as Moore’ s law has gradually become less effective and with the rise of the Internet of Things ( IoT), lightweight, miniaturized, and low-power edge devices have rapidly developed. The research focus on miniaturized TDCs for on-chip delay measurement has gradually shifted towards high-precision and low-power designs. Based on the Xilinx Virtex-6 XC6VLX240T FPGA development platform, a coarse measurement structure using a self-timed ring ( STR) instead of direct counting method and a fine measurement structure consisting of two symmetrical delay chains are proposed. The coarse measurement structure’ s STR is combined with the fine measurement’s symmetrical delay chains using edge coincidence detection units and latch units. The design results show that the range of the structure can reach 491 ns, with a resolution of 14. 8 ps and a maximum accuracy of 12. 9 ps. The power consumption is 0. 068 W, indicating that the proposed two-stage differential structure has the characteristics of high precision and low power consumption.

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