电子测量与仪器学报

黄正峰,杨潇,国欣祯,戚昊琛,鲁迎春,欧阳一鸣,倪天明,徐奇.基于 C 单元的抗干扰低功耗双边沿触发器[J].电子测量与仪器学报,2020,34(12):85-93

基于 C 单元的抗干扰低功耗双边沿触发器

Anti-interference low-power double edge-triggered flip-flop based on C-elements

DOI：

英文关键词:double edge-triggered flip-flop glitch lower power C-element clock tree circuit

基金项目:国家自然科学基金(61874156, 61874157, 61904001, 61904047)、安徽省自然科学基金(1908085QF272)资助项目

作者	单位
黄正峰	1. 合肥工业大学电子科学与应用物理学院
杨潇	1. 合肥工业大学电子科学与应用物理学院
国欣祯	1. 合肥工业大学电子科学与应用物理学院
戚昊琛	1. 合肥工业大学电子科学与应用物理学院
鲁迎春	1. 合肥工业大学电子科学与应用物理学院
欧阳一鸣	2. 合肥工业大学计算机与信息学院
倪天明	3. 安徽工程大学电气工程学院
徐奇	1. 合肥工业大学电子科学与应用物理学院

Author	Institution
Huang Zhengfeng	1. School of Electronic Science & Applied Physics,Hefei University of Technology
Yang Xiao	1. School of Electronic Science & Applied Physics,Hefei University of Technology
Guo Xinzhen	1. School of Electronic Science & Applied Physics,Hefei University of Technology
Qi Haochen	1. School of Electronic Science & Applied Physics,Hefei University of Technology
Lu Yingchun	1. School of Electronic Science & Applied Physics,Hefei University of Technology
Ouyang Yiming	2. School of Computer & Information,Hefei University of Technology
Ni Tianming	3. School of Electrical Engineering,Anhui Polytechnic University
Xu Qi	1. School of Electronic Science & Applied Physics,Hefei University of Technology

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中文摘要:

快速增长的功耗是 VLSI 设计中的重要问题,特别是输入信号中存在毛刺,双边沿触发器的功耗将会显著增大。为了有效降低功耗,提出了一种基于 C 单元的抗干扰低功耗双边沿触发器 AILP-DET,结构采用快速的 C 单元,不仅能够阻塞输入信号存在的毛刺,阻止触发器内部冗余跳变的发生,降低晶体管的充放电频率;而且增加了上拉-下拉路径,降低了其延迟。相比现有的双边沿触发器,AILP-DET 只在时钟边沿采样,有效降低了功耗。通过 HSPICE 仿真,与 10 种双边沿触发器相比较, AILPDET 仅仅增加了 7. 58%的延迟开销,无输入毛刺情况下总功耗平均降低了 261. 28%,有输入毛刺情况下总功耗平均降低了 46. 97%。详尽的电压温度波动分析表明,该双边沿触发器对电压、温度等波动不敏感。

英文摘要:

One of the paramount issues in the field of VLSI design is the rapid increase in power consumption. When the input signal is interfered and glitches occur, the power consumption of the double edge-triggered flip-flop (DETFF) will increase significantly. In order to effectively reduce the power consumption, this paper proposed an anti-interference low-power double edge-triggered flip-flop based on C-elements. The improved C-element is used in this DETFF. One side, it effectively blocks the glitches in the input signal, prevents redundant transitions inside the DETFF, and reduces the charge and discharge frequency of the transistor. The C-element also adds pullup and pull-down paths, reducing its latency. Compared with other existing DETFFS, the DETFF proposed in this paper only flips once on the clock edge, which effectively reduces power consumption. The HSPICE is used to simulate the proposed DETFF and the other 10 DETFFs, AILP-DET only increased the delay overhead by 7. 58%, the total power consumption is reduced by an average of 261. 28% without input glitches, and the average power consumption is reduced by 46. 97% with input glitches. Detailed voltage and temperature variations analysis indicate that the proposed DETFF features are less sensitive to voltage and temperature variations.

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