The Time-to-Digital Converter (TDC) is a device designed to convert the continuous analog value of time interval between signal pulses into discrete digital values. The tapped-delay-line time-to-digital converter (TDL-TDC) is commonly implemented using the internal carry chain resources of Field Programmable Gate Array (FPGA) chips. However, the delay time of each delay bin in the TDL-TDC is significantly impacted by variations in operating temperature. Currently, methods of TDC calibration , such as code density calibration, linear compensation, or high-order Taylor function fitting, struggle to accurately model the changing delay times of individual bins within a long delay line under varying temperature conditions. To maintain the required precision of TDC operations, a neural network calibration based on Multilayer Perceptron (MLP) is proposed. This method utilizes delay time and corresponding temperature data from 128 delay bins in the delay line as training data to construct a four-layer MLP. By feeding back temperature information when working, the network can independently calculate delay time of differernt bin to determine the time interval between signal pulses. Experimental results confirm the effectiveness of the network calibration in compensating for temperature variations, with the potential for deployment across different FPGA chips. The network achieves an accuracy of 91%, and the resolution of TDC is 34ps.