国家自然科学基金(61874156, 61874157, 61904001, 61904047) , 安徽省自然科学基金(1908085QF272);
One of the paramount issues in the field of VLSI design is the rapid increase in power consumption. When the input signal is interfered and glitches occur, the power consumption of the double edge-triggered flip-flop (DETFF) will increase significantly. In order to effectively reduce the power consumption, this paper proposed an anti-interference low-power double edge-triggered flip-flop based on C-elements. The improved C-element is used in this DETFF. One side, it effectively blocks the glitches in the input signal, prevents redundant transitions inside the DETFF, and reduces the charge and discharge frequency of the transistor. The C-element also adds pull-up and pull-down paths, reducing its latency. Compared with other existing DETFFS, the DETFF proposed in this paper only flips once on the clock edge, which effectively reduces power consumption. This paper uses HSPICE to simulate the proposed DETFF and the other 10 DETFFs, AILP-DET only increased the delay overhead by 7.58%, the total power consumption is reduced by an average of 261.28% without input glitches, and the average power consumption is reduced by 46.97% with input glitches. Detailed voltage and temperature variations analysis indicate that the proposed DETFF features less sensitive to voltage and temperature variations.