| 张镕方,年夫顺,袁国平.去耦电容阻抗参数测试与夹具去嵌入技术[J].电子测量与仪器学报,2026,40(4):135-143 |
| 去耦电容阻抗参数测试与夹具去嵌入技术 |
| Decoupling capacitor impedance parameter testing andfixture de-embedding technology |
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| DOI： |
| 中文关键词: 电源分配网络 去耦电容 夹具去嵌入 阻抗参数提取 |
| 英文关键词:PDN decoupling capacitor fixture de-embedding impedance parameter extraction |
| 基金项目:国家自然科学基金（U24B6013）项目资助 |
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| Author | Institution |
| Zhang Rongfang | School of Instrument and Electronics, North University of China, Taiyuan 030051, China |
| Nian Fushun | 1.School of Instrument and Electronics, North University of China, Taiyuan 030051, China;
2.Ceyear Technologies Co.，Ltd., Qingdao 266555, China |
| Yuan Guoping | Ceyear Technologies Co.，Ltd., Qingdao 266555, China |
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| 中文摘要: |
| 纳米级半导体工艺下芯片电压已低至0.8 V，部分芯片功耗突破700 W，最高电流超过2 000 A，对支撑芯片工作的电源分配网络提出了宽频带范围、超低阻抗、低损耗等要求。电源分配网络当中去耦电容的本征参数是优化设计的关键，为了获取精确的电容参数模型，用于电源分配网络电源完整性仿真与分析，提出了基于矢量网络分析仪的高精度宽带去耦电容本征参数提取方法，引入矢量拟合和误差修正方法，解决了迹线噪声导致的测试轨迹过零问题，并提取了去耦电容本征参数。搭建了实验系统，设计了夹具并实施多级校准和夹具去嵌入，测试频率范围500 Hz~3 GHz，电容容值误差≤5%，等效串联电阻误差≤3%，等效串联电感误差≤6%，去耦电容本征参数测试值与参考值一致，代入等效模型得到的阻抗曲线与测量结果一致。该方法可高效可靠地获取去耦电容本征参数，为电源分配网络优化设计提供可靠数据，对支撑算力网络和数字系统等供电系统研发具有重要的工程意义。 |
| 英文摘要: |
| In nanoscale semiconductor manufacturing processes, the operating voltage of chips has been reduced to as low as 0.8 V, while the power consumption of some chips exceeds 700 W and the peak current exceeds 2 000 A. These trends impose stringent requirements on the power distribution network (PDN) that supports chip operation, including wide frequency bandwidth, ultra-low impedance, and low power loss. The intrinsic parameters of decoupling capacitors within the PDN are critical to its optimal design. To obtain accurate capacitor parameter models for PDN power integrity simulation and analysis, this paper proposes a high-precision broadband method for extracting the intrinsic parameters of decoupling capacitors based on a vector network analyzer (VNA). Vector fitting and error correction techniques are introduced to address the zero-crossing issue in test trajectories caused by trace noise, and the intrinsic parameters of the decoupling capacitors are extracted. An experimental system is constructed, with fixtures designed and multi-stage calibration and fixture de-embedding implemented. The test frequency range is 500 Hz to 3 GHz, achieving a capacitance error of ≤5%, an equivalent series resistance (ESR) error of ≤3%, and an equivalent series inductance (ESL) error of ≤6%. The measured intrinsic parameters of the decoupling capacitors are consistent with the reference values, and the impedance curves derived from substituting these parameters into the equivalent model align with the measured results. This method enables efficient and reliable extraction of the intrinsic parameters of decoupling capacitors, providing robust data for the optimal design of PDN and holding significant engineering value for the development of power supply systems supporting computing networks and digital systems. |
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