| 尹卓异,员方,崔翰文,刘胜,张召富,何小元.半导体制造及封装中的翘曲测量方法与应用进展[J].电子测量与仪器学报,2026,40(1):1-19 |
| 半导体制造及封装中的翘曲测量方法与应用进展 |
| Advances in warpage measurement methods and applications insemiconductor manufacturing and packaging |
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| DOI： |
| 中文关键词: 半导体 制造 先进封装 翘曲 测量 |
| 英文关键词:semiconductor manufacturing advanced packaging warpage measurement |
| 基金项目:国家自然科学基金（11827801,92473202）、电子制造与封装集成湖北省重点实验室开放课题（EMPI2025010）项目资助 |
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| Author | Institution |
| Yin Zhuoyi | 1.School of Physics, Nanjing University of Science and Technology, Nanjing 210094, China; 2.Hubei Key Laboratory of
Electronic Manufacturing and Packaging Integration，Wuhan University, Wuhan 430072,China |
| Yuan Fang | School of Civil
Engineering, Suzhou University of Science and Technology, Suzhou 215009, China |
| Cui Hanwen | 2.Hubei Key Laboratory of
Electronic Manufacturing and Packaging Integration，Wuhan University, Wuhan 430072,China; 4.School of Integrated
Circuits, Wuhan University, Wuhan 430072, China |
| Liu Sheng | 2.Hubei Key Laboratory of
Electronic Manufacturing and Packaging Integration，Wuhan University, Wuhan 430072,China; 4.School of Integrated
Circuits, Wuhan University, Wuhan 430072, China |
| Zhang Zhaofu | 2.Hubei Key Laboratory of
Electronic Manufacturing and Packaging Integration，Wuhan University, Wuhan 430072,China; 4.School of Integrated
Circuits, Wuhan University, Wuhan 430072, China |
| He Xiaoyuan | School of Civil Engineering,
Southeast University, Nanjing 210096, China |
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| 摘要点击次数: 938 |
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| 中文摘要: |
| 随着集成电路技术的不断发展，先进制造工艺和先进封装技术在提升芯片性能与集成度的同时，大尺寸结构、高密度互连与多芯片叠层也使翘曲等可靠性问题更加突出，增加了失效风险。为提高半导体工艺的稳定性与良率，翘曲的精确测量与分析已成为工艺控制的关键环节。系统综述了半导体封装中翘曲的定义、测量方法及最新研究进展。首先依据国内外标准阐明翘曲的概念及测量规范；随后介绍接触式、激光扫描、阴影莫尔、干涉、条纹投影和数字图像相关等主要测量方法，并比较其原理、优势与局限。统计显示，阴影莫尔法应用最为广泛，而数字图像相关方法凭借应变与热膨胀系数测量能力及良好可扩展性正快速增长；条纹投影方法的应用比例也因其高灵活性持续上升。最后，总结了国内外商业化翘曲测量设备在精度、视场与测量原理方面的现状，并提出国产设备的改进方向。为翘曲测量方法的选型及半导体工艺优化提供了参考，促进测量技术与产业的发展。 |
| 英文摘要: |
| With the continuous advancement of integrated circuit technology, advanced manufacturing and packaging have greatly enhanced chip performance and integration density. However, large-scale structures, high-density interconnects, and multi-chip stacking also intensify reliability issues such as warpage, raising the risk of failure. To improve the stability and yield of semiconductor processes, accurate warpage measurement and analysis have become essential for process control. This paper provides a systematic review of the definition, measurement methods, and recent progress related to warpage in semiconductor packaging. The concept of warpage and the corresponding measurement standards are first clarified based on domestic and international specifications. Major measurement techniques—including contact methods, laser scanning, shadow moir, interferometry, fringe projection, and digital image correlation—are then introduced and compared in terms of their principles, advantages, and limitations. Literature statistics indicate that shadow moir is the most widely used method, while digital image correlation is rapidly growing due to its capability for strain and coefficient of thermal expansion measurement and strong scalability; fringe projection is also increasingly adopted for its high flexibility. Finally, this paper summarizes the current status of commercial warpage-measurement systems in terms of accuracy, field of view, and measurement principles, and outlines potential improvement directions for domestic instruments. This review aims to support the selection of warpage-measurement methods and the optimization of semiconductor processes, promoting the development of measurement technologies and the broader industry. |
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