| 翁毅钦,方宇龙,钟杨源,吴雨帆,阴亚东.面向时间寄存器型模拟时域电路的自动校准电路[J].电子测量与仪器学报,2026,40(2):244-251 |
| 面向时间寄存器型模拟时域电路的自动校准电路 |
| Automatic calibration circuit for time register-based analog time-domain circuits |
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| DOI： |
| 中文关键词: 时间寄存器 自动校准 PVT变化 模拟时域信号处理电路 |
| 英文关键词:time register automatic calibration PVT variation ATDSPC |
| 基金项目:福建省工业引导性(重点)项目(2024H0006)、福建省对外合作项目(2020I0005)、福建省高校产学合作项目(2020Y4017)资助 |
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| Author | Institution |
| Weng Yiqin | Department of Physics and Information Engineering, Fuzhou University, Fuzhou 350116, China |
| Fang Yulong | Department of Physics and Information Engineering, Fuzhou University, Fuzhou 350116, China |
| Zhong Yangyuan | Fujian Fuxin Electronics Technology Co., Ltd., Fuzhou 350100,China |
| Wu Yufan | Department of Physics and Information Engineering, Fuzhou University, Fuzhou 350116, China |
| Yin Yadong | Department of Physics and Information Engineering, Fuzhou University, Fuzhou 350116, China |
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| 摘要点击次数: 279 |
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| 中文摘要: |
| 基于时间寄存器的模拟时域信号处理电路(简称为模拟时域电路)是当前研究热点，具有低功耗、抗干扰能力强等优点，但仍存在时间寄存器溢出问题。提出并验证了一种自动校准电路，可有效解决模拟时域电路因工艺-电压-温度（PVT）造成的时间寄存器溢出问题。该电路主要由时间寄存器、数字控制算法、时间误差检测器和可编程电流源构成。其利用数字控制算法并结合时间误差检测器能够实时检测时间寄存器存在溢出风险；当检测到存在溢出风险时，其将自适应地修改可编程偏置电流以调整时间寄存器中电容放电速度从而消除风险。该校准电路采用SMIC 0.18 μm CMOS工艺进行设计和流片。芯片测试结果表明，未使用该校准电路时，温度和电源电压波动时时间寄存器存在溢出风险，造成了模拟时域信号时序偏差大于15%；当使用该校准电路时，时间寄存器可保持稳定，时序偏差小于1%。该设计可集成至时间 数值转换器和全数字锁相环等模拟时域信号处理电路中以提升电路鲁棒性。 |
| 英文摘要: |
| The analog time-register-based time-domain signal processing circuit (refer as analog time-domain circuits for short) is a current research hotspot, featuring lots of merits such as low power consumption and strong anti-interference ability. However, it suffers the time register-overflowing issue. This paper proposes and verifies an automatic calibration circuit that can effectively solve the problem of time register overflow caused by process-voltage-temperature (PVT) variations in analog time-domain circuits. The circuit mainly consists of a time register, a digital control algorithm, a time error detector, and a programmable current source. By using the digital control algorithm in combination with the time error detector, it can detect in real time whether the time register is at risk of overflow. When an overflow risk is detected, it will adaptively modify the programmable bias current to adjust the capacitor discharging speed in the time register therefore eliminate the risk. The calibration circuit is designed and fabricated using the SMIC 0.18 μm CMOS process. The chip test results show that, without using this calibration circuit, when the temperature and power supply voltage fluctuate, the time register bears the overflowing risk and a time deviation of the analog time-domain signal greater than 15% is observed. When using this calibration circuit, the time register runs stably, and the time deviation is less than 1%. This design can be integrated into kinds of analog time-domain signal processing circuits such as time-to-digital converters and all-digital phase-locked loops, to enhance their robustness. |
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