电子测量与仪器学报

许玥,谢杰,曾中明,张宝顺,吴东岷.面向FPGA-TDL-TDC的延迟时间逐位校准网络[J].电子测量与仪器学报,2024,38(7):89-96

面向FPGA-TDL-TDC的延迟时间逐位校准网络

Bin-by-bin network calibration for delay time of FPGA-TDL-TDC

DOI：

中文关键词: 现场可编程逻辑门阵列抽头延迟链时间数字转换器多层感知机神经网络校准

英文关键词:FPGA TDL-TDC multilayer perceptron neural network calibration

基金项目:国家重点研发计划（2021YFB3202202）项目资助

作者	单位
许玥	1.中国科学技术大学纳米技术与纳米仿生学院合肥230026； 2.中国科学院苏州纳米技术与纳米仿生研究所苏州215123
谢杰	中国科学技术大学纳米技术与纳米仿生学院合肥230026
曾中明	1.中国科学技术大学纳米技术与纳米仿生学院合肥230026； 2.中国科学院苏州纳米技术与纳米仿生研究所苏州215123
张宝顺	1.中国科学技术大学纳米技术与纳米仿生学院合肥230026； 2.中国科学院苏州纳米技术与纳米仿生研究所苏州215123
吴东岷	1.中国科学技术大学纳米技术与纳米仿生学院合肥230026； 2.中国科学院苏州纳米技术与纳米仿生研究所苏州215123

Author	Institution
Xu Yue	1.School of Nano-Tech and Nano-Bionics, University of Science and Technology of China, Hefei 230026, China; 2.Suzhou Institute of Nano-Tech and NanoBionics, Chinese Academy of Sciences, Suzhou 215123, China
Xie Jie	School of Nano-Tech and Nano-Bionics, University of Science and Technology of China, Hefei 230026, China
Zeng Zhongming	1.School of Nano-Tech and Nano-Bionics, University of Science and Technology of China, Hefei 230026, China; 2.Suzhou Institute of Nano-Tech and NanoBionics, Chinese Academy of Sciences, Suzhou 215123, China
Zhang Baoshun	1.School of Nano-Tech and Nano-Bionics, University of Science and Technology of China, Hefei 230026, China; 2.Suzhou Institute of Nano-Tech and NanoBionics, Chinese Academy of Sciences, Suzhou 215123, China
Wu Dongmin	1.School of Nano-Tech and Nano-Bionics, University of Science and Technology of China, Hefei 230026, China; 2.Suzhou Institute of Nano-Tech and NanoBionics, Chinese Academy of Sciences, Suzhou 215123, China

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中文摘要:

时间数字转换器（TDC）是一种将信号脉冲之间时间间隔的连续模拟量转换为离散数字量的设备。基于现场可编程逻辑门阵列（FPGA）内部进位链资源实现抽头延迟链-时间数字转换器（TDL-TDC）的方法被广泛应用，但TDL-TDC中每个延迟单元的延迟时间数值受运行温度变化的影响较大，目前使用码密度测试、线性补偿或高阶泰勒函数拟合等的TDC校准方法不能很好地拟合复杂温度变化情况下长延迟链中各单元延迟时间的变化趋势。为继续满足TDC工作精度要求，提出了一种基于多层感知机（MLP）的神经网络校准方案，以延迟链中128个延迟单元的延迟时间数据和相应温度数据作为训练样本建立4层MLP。工作时通过反馈当前运行温度信息，可以独立给出每个延迟单元的延迟时间数值，以用于计算待测脉冲之间的时间间隔。实验验证了校准网络对温度变化的补偿作用，该网络可以移植于不同的FPGA芯片。测量得到校准网络的准确率为91%，实现TDC分辨率为34 ps。

英文摘要:

The time-to-digital converter (TDC) is a device designed to convert the continuous analog value of time interval between signal pulses into discrete digital values. The tapped-delay-line time-to-digital converter (TDL-TDC) is commonly implemented using the internal carry chain resources of field programmable gate array (FPGA) chips. However, the delay time of each delay bin in the TDL-TDC is significantly impacted by variations in operating temperature. Currently, methods of TDC calibration, such as code density calibration, linear compensation, or high-order Taylor function fitting, struggle to accurately model the changing delay times of individual bins within a long delay line under varying temperature conditions. To maintain the required precision of TDC operations, a neural network calibration based on multilayer perceptron (MLP) is proposed. This method utilizes delay time and corresponding temperature data from 128 delay bins in the delay line as training data to construct a four-layer MLP. By feeding back temperature information when working, the network can independently calculate delay time of different bin to determine the time interval between signal pulses. Experimental results confirm the effectiveness of the network calibration in compensating for temperature variations, with the potential for deployment across different FPGA chips. The network achieves an accuracy of 91%, and the resolution of TDC is 34 ps.

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