| 张锦,刘政辉,扈啸,胡春媚.面向自主芯片频率扫描实速测试的扫描链分析[J].电子测量与仪器学报,2024,38(3):122-132 |
| 面向自主芯片频率扫描实速测试的扫描链分析 |
| Scan chain analysis for at-speed test of frequency scanning of autonomous chip |
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| DOI： |
| 中文关键词: 实速测试 扫描链 芯片测试 测试向量 路径延时 |
| 英文关键词:at-speed test scan chain chip test test vector path delay |
| 基金项目:mail_zhangjin@163.com |
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| Author | Institution |
| Zhang Jin | School of Computer and Communication Engineering, Changsha University of Science and Technology, Changsha 410076,China |
| Liu Zhenghui | School of Computer and Communication Engineering, Changsha University of Science and Technology, Changsha 410076,China |
| Hu Xiao | 2.College of Computer Science and Technology, National University of Defense Technology, Changsha 410073,China;
3.Key Laboratory of Advanced Microprocessor Chips and Systems, Changsha 410073,China |
| Hu Chunmei | 2.College of Computer Science and Technology, National University of Defense Technology, Changsha 410073,China;
3.Key Laboratory of Advanced Microprocessor Chips and Systems, Changsha 410073,China |
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| 摘要点击次数: 237 |
| 全文下载次数: 1998 |
| 中文摘要: |
| 随着芯片工艺的不断升级，芯片设计的频率不断提高，时延故障是引起高速芯片失效的重要因素。在硅后验证阶段，由于缺乏一种对芯片全局路径延时测量的手段，传统构建延时测量电路的方式仅能得到特定关键路径的延时变化情况，在芯片失效时无法进行全面的路径延时分析。本文提出一种基于扫描链的频率扫描实速测试方法对芯片内部大量时序路径的延时进行测量并获取时序裕量。针对生成测试向量时间长，依赖专业测试设备的问题，在自研硬件平台上通过自生成多频率测试向量以及改进数据校验算法成功实现了频率扫描实速测试，对芯片测量的路径延时误差在8 ps左右。通过对不同芯片在不同温度下的实验验证了该方法对路径延时表征的有效性，为今后通过延时参数对高速芯片进行环境适应性分析、寿命预测等研究提供了一种快捷有效的方法。 |
| 英文摘要: |
| With the continuous advancement of chip technology and the increasing frequency of chip design, delay faults have become an important factor leading to the failure of high-speed chips. In the post-silicon validation stage, due to the lack of a method for measuring the global path delay of chips, the traditional method of constructing delay measurement circuits can only obtain the delay variation of specific critical paths, and comprehensive path delay analysis cannot be conducted when the chip fails. This paper proposes a frequency sweeping at-speed testing method based on scan chains to measure the delay of a large number of timing paths inside the chip and obtain the timing margin. Addressing the issues of long test vector generation time and reliance on specialized testing equipment, frequency sweeping at-speed testing was successfully implemented on a self-developed hardware platform through the generation of multi-frequency test vectors and an improved data verification algorithm. The measurement error of the chip’s path delay is around 8 ps. Experimental verification on different chips at different temperatures confirmed the effectiveness of this method in characterizing path delay, providing a fast and effective method for future research on environmental adaptability analysis and lifetime prediction of high-speed chips through delay parameters. |
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