| 胡雪南,姜雪松,程远杰,刘景鑫,李添.基于Farrow结构的多径信道小数时延模拟方法[J].电子测量与仪器学报,2024,38(8):237-244 |
| 基于Farrow结构的多径信道小数时延模拟方法 |
| Multipath channel fractional delay simulation method based on Farrow structure |
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| DOI： |
| 中文关键词: 信道模拟器 小数时延 Farrow滤波器 FPGA |
| 英文关键词:channel emulator fractional delay Farrow filter FPGA |
| 基金项目: |
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| Author | Institution |
| Hu Xuenan | China Mobile Research Institute Co., Ltd., Beijing 100053, China; |
| Jiang Xuesong | China Mobile Research Institute Co., Ltd., Beijing 100053, China; |
| Cheng Yuanjie | China Mobile Research Institute Co., Ltd., Beijing 100053, China; |
| Liu Jingxin | Transcom Instruments, Shanghai 201600, China |
| Li Tian | Transcom Instruments, Shanghai 201600, China |
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| 摘要点击次数: 17 |
| 全文下载次数: 85 |
| 中文摘要: |
| 在信道模拟的过程中，为了更加逼近真实的通信场景，信道模拟器需要达到非常高的多径时延精确度，这对信道模拟器的仿真能力提出了更高的要求。信道模型的处理和加载任务通常在数字基带内实现，其时钟分辨率是有限的，需要借助Farrow结构小数滤波器来实现更高时延精度。为实现超高精度的时延模拟，根据信道模拟算法的特点，采取DSP与分布式乘法混用的方式对Farrow结构小数滤波器进行了优化设计。设计方案在创远信科的信道模拟器Pathrrot-X80上执行了验证和测试。结果表明，改进的Farrow滤波器的结构设计大幅度降低了FPGA计算资源的消耗，使得小数延时算法能够在高时延精度和低资源开销之间达到平衡；多径时延精度在低频段的测试结果与理论推算基本吻合，满足信道模拟所期望的0.1 ns的要求；时延精度在高频段与理论推算出入较大，为了达到更好的性能或更小的信号失真，可以考虑提升滤波器阶数，或寻找更优的系数计算算法。 |
| 英文摘要: |
| It is needed to achieve very high multipath delay accuracy to better approximate the real communication scenario in the process of channel simulation, which puts higher requirements on the simulation ability of the channel emulator. Channel models is processed and loaded usually within the digital baseband, and so the clock resolution is limited. It is necessary to make use of Farrow structured fractional filters to achieve higher delay accuracy. In according to the characteristics of channel simulation algorithms, the Farrow structure fractional filter was designed and optimized by mixing DSP and distributed multiplication to achieve ultra-high precision delay simulation. The design scheme was validated and tested on the TRANSCOM Pathrot X80 channel emulator. The results show that,the improved Farrow filter′s structural design significantly reduces the consumption of FPGA computing resources, enabling the fractional delay algorithm to achieve a balance between high delay accuracy and low resource overhead; the multipath delay accuracy is consistent with theoretical calculations in the low frequency range, meeting the expected 0.1 ns requirement for channel simulation; the delay accuracy differs significantly from theoretical calculations in the high-frequency range. In order to achieve better performance or reduce signal distortion, it can be considered to increase the order of the filter or find a better coefficient calculation algorithm. |
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