陈珍海,于宗光,魏敬和,苏小波,万书芹.采用1.75 Gbps串行发送器的低功耗14位125 MSPS ADC[J].电子测量与仪器学报,2017,31(1):132-138
采用1.75 Gbps串行发送器的低功耗14位125 MSPS ADC
Low power 14 bit 125 MSPS ADC with 1.75 Gbps serial transmitter
  
DOI:10.13382/j.jemi.2017.01.019
中文关键词:  流水线模数转换器  运算放大器  电流模发送器  低功耗
英文关键词:pipelined analog to digital converter  operation amplifier  current mode transmitter  low power
基金项目:国家自然科学基金(61474092)资助项目
作者单位
陈珍海 1.中国电子科技集团第五十八研究所无锡214035;3.黄山学院信息工程学院黄山245041 
于宗光 1.中国电子科技集团第五十八研究所无锡214035;2.西安电子科技大学微电子学院西安710071 
魏敬和 中国电子科技集团第五十八研究所无锡214035 
苏小波 1.中国电子科技集团第五十八研究所无锡214035;2.西安电子科技大学微电子学院西安710071 
万书芹 中国电子科技集团第五十八研究所无锡214035 
AuthorInstitution
Chen Zhenhai 1. No.58 Research Institute, China Electronic Technology Group Corporation, Wuxi 214035, China; 3. School of Information Engineering, Huangshan University, Huangshan 245041, China 
Yu Zongguang 1. No.58 Research Institute, China Electronic Technology Group Corporation, Wuxi 214035, China; 2. School of Microelectronics, Xidian University, Xi’an 710071, China 
Wei Jinghe No.58 Research Institute, China Electronic Technology Group Corporation, Wuxi 214035, China 
Su Xiaobo 1. No.58 Research Institute, China Electronic Technology Group Corporation, Wuxi 214035, China; 2. School of Microelectronics, Xidian University, Xi’an 710071, China 
Wan Shuqin No.58 Research Institute, China Electronic Technology Group Corporation, Wuxi 214035, China 
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中文摘要:
      提供了一种适宜于多通道集成的低功耗、小面积14位125 MSPS流水线模数转换器(ADC)。该ADC基于开关电容流水线ADC结构,采用无前端采样保持放大器、4.5位第一级子级电路、电容逐级缩减和电流模串行输出技术设计并实现。各级流水线子级电路中所用运算放大器使用改进的“米勒”补偿技术,在不增加电流的条件下实现了更大带宽,进一步降低了静态功耗;采用1.75 Gbps串行数据发送器,数据输出接口减少到2个。该ADC电路采用0.18 μm 1P5M 1.8 V CMOS工艺实现,测试结果表明,该ADC电路在全速采样条件下对于10.1 MHz的输入信号得到的SNR为72.5 dBFS, SFDR为83.1 dB,功耗为241 mW,面积为1.3 mm×4 mm。
英文摘要:
      A low power, small die size 14 bit 125 MSPS pipelined ADC is presented. Switched capacitor pipelined ADC architecture is chosen for the 14 bit ADC. In order to achieve low power and compact die size, the sample and hold amplifier is removed, the 4.5 bit sub stage circuit is used in the first pipelined stage. The capacitor down scaling technique is introduced, and the current mode serial transmitter is used. A modified miller compensation technique is used in the operation amplifiers in the pipelined sub stage circuits, which offers a large bandwidth without additional current consumption. A 1.75 Gbps transmitter is introduced to drive the digital output code, which only needs 2 output pins. The ADC is fabricated in 0.18 μm 1.8 V 1P5M CMOS technology. The test results show that the 14 bit 125 MSPS ADC achieves the SNR of 72.5 dBFS and SFDR of 83.1 dB, with 10.1 MHz input at full sampling speed, while consumes the power consumption of 241 mW and occupies an area of 1.3 mm×4 mm.
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