电子测量与仪器学报

肖寅东,曾宇通,刘科,胡聪.基于 XGBoost 的模拟集成电路测试参数优化方法[J].电子测量与仪器学报,2023,37(4):61-68

基于 XGBoost 的模拟集成电路测试参数优化方法

Test parameter optimization method for analog IC testing by XGBoost

DOI：

英文关键词:machine learning XGBoost integrated circuit testing test cost test escape

基金项目:国家自然科学基金(61871089)、广西自动检测技术与仪器重点实验室开放基金(YQ201202)项目资助

作者	单位
肖寅东	1. 电子科技大学自动化工程学院
曾宇通	1. 电子科技大学自动化工程学院
刘科	1. 电子科技大学自动化工程学院
胡聪	2. 桂林电子科技大学广西自动检测技术与仪器重点实验室

Author	Institution
Xiao Yindong	1. School of Automation Engineering, University of Electronic Science and Technology of China
Zeng Yutong	1. School of Automation Engineering, University of Electronic Science and Technology of China
Liu Ke	1. School of Automation Engineering, University of Electronic Science and Technology of China
Hu Cong	2. Guangxi Key Laboratory of Automatic Testing Technology and Instruments, Guilin University of Electronic Technology

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中文摘要:

随着集成电路的规模不断扩大,其测试成本随测试时间的增长而不断提高,如何优化测试参数是一个重要课题。模拟集成电路测试中,测试参数间存在非线性隐式依赖,使得直接揭示其相互关系并进行测试方法优化非常困难。本文基于 XGBoost 决策树模型提出了一种优化模拟集成电路测试参数数目的方法,该方法探索不同测试参数间的相互表征能力,在测试序列中依次删减可被良好表达的测试参数,在保证一定逃逸率的条件下达到缩短测试时间的目的。本文讨论了故障数目、特征重要性和 SHAP 值 3 种评估测试参数间表征能力的指标,并对两类模拟集成电路测试数据集进行了实验,结果表明故障数目是一种优秀的评估指标,可在测试逃逸率不超过 20 PPM 的条件下实现 25%的测试参数优化。

英文摘要:

As the scale of integrated circuits continues to increase and their test cost increases with test time, the optimization of the test terms is an important topic. The existence of nonlinear implicit dependencies among test parameters in analog integrated circuit testing makes it very difficult to directly reveal their interrelationships and perform test method optimization. In this paper, we propose a method to optimize the number of test parameters of analog integrated circuits based on the XGBoost decision tree model, which explores the mutual characterization ability among different test parameters and sequentially deletes the test parameters that can be well expressed in the test sequence to achieve the purpose of shortening the test time under the condition of ensuring a certain escape rate. The paper discusses three metrics to evaluate the inter-representation capability of test parameters, such as the number of faults, feature importance and SHAP value, and conducts experiments on two types of analog IC test datasets. The results show that the number of faults is an excellent evaluation metric that can achieve 25% test parameter optimization under the condition that the test escape rate does not exceed 20 PPM.

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