电子测量与仪器学报

刘伟,郭尚尚,商世广.用于 CZT 探测器前端的数字自校准 SAR-ADC 设计[J].电子测量与仪器学报,2022,36(9):167-173

用于 CZT 探测器前端的数字自校准 SAR-ADC 设计

Design of SAR-ADC with digital self-calibration for CZT detectors front-ends

DOI：

英文关键词:detector analog-to-digital converter calibration least mean square (LMS)

基金项目:陕西省自然科学基础研究计划（2020JM 583）、陕西省教育厅重点科学研究计划协同创新项目（21JY039）资助

作者	单位
刘伟	1.西安邮电大学电子工程学院
郭尚尚	1.西安邮电大学电子工程学院
商世广	1.西安邮电大学电子工程学院

Author	Institution
Liu Wei	1.School of Electronic Engineering, Xi′an University of Posts and Telecommunications
Guo Shangshang	1.School of Electronic Engineering, Xi′an University of Posts and Telecommunications
Shang Shiguang	1.School of Electronic Engineering, Xi′an University of Posts and Telecommunications

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中文摘要:

为了满足碲锌镉(CZT)探测器前端读出系统对模数转换器(ADC)的特殊需求,设计实现了一款 12 bit 1. 6 MS / s 的前台数字自校准逐次逼近型(SAR)ADC。采用先校准后正常输出的工作方式以提高数据转换的实时性,校准模式下,SAR-ADC 核心部分对差分斜坡输入电压注入低幅值扰动,再利用最小均方(LMS)自适应算法在数字域对亚二进制电容权重进行校准并固定;正常工作模式下,按照已经校准的权重值正常输出数字码。搭建数模混合仿真平台进行仿真验证,结果表明,当时钟信号频率为 20 MHz,输入信号频率为 239. 1 kHz 时,校准后与校准前相比,SAR-ADC 的信噪失真比( signal-to-noise and distortion ratio, SNDR)由 45. 59 dB 提升到了 72. 35 dB,有效位数(effective number of bit, ENOB)由 7. 28 bit 提升到了 11. 73 bit,SAR-ADC 性能明显提升,前端读出电路与 SAR-ADC 的联合线性度 δ 为-0. 29% ~ 0. 34%,能够满足 CZT 探测器前端读出系统的使用需求。

英文摘要:

In order to meet the special requirements of the front-end readout system of cadmium zine telluride (CZT) detector for analog to digital converter (ADC), a foreground digital self-calibration successive approximation register (SAR) ADC with 12 bit 1. 6 MS / s is presented. The working mode of calibration followed by output is adopted to improve the real-time performance of data conversion. In the calibration mode, the core part of SAR-ADC injects low amplitude disturbance to the differential ramp input voltage, then uses the least mean square (LMS) adaptive algorithm to calibrate and fix the Sub-radix-2 capacitance weight in the digital domain. In the normal working mode, the digital code is output normally according to the calibrated weight value. A digital-analog hybrid simulation platform is built for simulation and verification. The results show that when the clock signal frequency is 20 MHz and the input signal frequency is 239. 1 kHz, the signal-to-noise and distortion ratio (SNDR) of SAR-ADC after calibration is increased from 45. 59 dB to 72. 35 dB, and the effective number of bit (ENOB) is increased from 7. 28 bit to 11. 73 bit. The performance of SAR-ADC is obviously improved, and the linearity δ between front-end readout circuit and SAR-ADC is-0. 29% ~ 0. 34%, which can meet the requirements of CZT detector front-end readout system.

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