| 丁博文,苗 澎,黎 飞,王 欢,谷伟齐.500 MS / s 12 位流水线 ADC 的设计研究[J].电子测量与仪器学报,2022,36(3):130-138 |
| 500 MS / s 12 位流水线 ADC 的设计研究 |
| Design research of 500 MS / s 12 bit pipeline ADC |
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| DOI： |
| 中文关键词: 低压运算放大器 流水线 ADC 级间增益误差 电容失配 |
| 英文关键词:low voltage opamp pipeline ADC inter-stage gain error capacitor mismatch |
| 基金项目:国家重点研发计划(2018YFB2003302) 项目资助 |
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| Author | Institution |
| Ding Bowen | 1.School of Information Science and Engineering, Southeast University, |
| Miao Peng | 1.School of Information Science and Engineering, Southeast University, |
| Li Fei | 1.School of Information Science and Engineering, Southeast University, |
| Wang Huan | 1.School of Information Science and Engineering, Southeast University, |
| Gu Weiqi | 1.School of Information Science and Engineering, Southeast University, |
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| 中文摘要: |
| 在超高速高精度模数转换器(ADC)设计中,低压运算放大器及其数字辅助校准算法至关重要。 基于 40 nm CMOS 工
艺、工作电压 1. 1 V,设计了一款 500 MS / s、12 位流水线 ADC。 系统采用前端无采保结构及低压级间运算放大器以降低系统功
耗。 本文提出了一种基于数字检测的算法校准级间增益和电容失配误差,使用较小的面积和功耗有效提高了 ADC 的整体性
能。 本数字校准方案将 ADC 的差分非线性(DNL)和积分非线性(INL)从 2. 4 LSB 和 5. 9 LSB 降低为 1. 7 LSB 和 0. 8 LSB。 对
于 74. 83 MHz 的正弦信号,校准技术分别实现了 63. 14 dB 的信号-失真噪声比(SNDR)和 75. 14 dB 的无杂散动态范围(SFDR),
功耗为 123 mW,满足设计指标,证明了带有数字校正的低压流水线 ADC 设计的有效性。 |
| 英文摘要: |
| Low voltage operational amplifiers and their digitally assisted calibration algorithms are critical in the design of ultra-high
speed, high resolution analog-to-digital converters (ADCs). A 500 MS / s, 12-bit pipeline ADC based on a 40 nm CMOS process and
operating voltage of 1. 1 V has been proposed. This ADC adopts a sample-and-hold (SHA) less front-end structure and low-voltage interstage operational amplifiers (opamp) to reduce power consumption. A foreground calibration algorithm using digital detection is designed
for gain error and capacitance mismatch calibration, effectively improving the overall performance of the ADC using smaller area and
power consumption. This digital calibration scheme improves the differential nonlinearity (DNL) and integral nonlinearity (INL) of the
ADC from 2. 4 LSB and 5. 9 LSB to 1. 7 LSB and 0. 8 LSB. for a 74. 83 MHz sinusoidal signal, the calibration technique achieves a
signal-to-distortion noise ratio (SNDR) of 63. 14 dB and a spurious-free dynamic range ( SFDR) of 75. 14 dB, respectively, with a
power consumption of 123 mW, which meets the design targets and demonstrates the effectiveness of a low-voltage pipeline ADC design
with digital correction. |
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