詹文法,彭登辉,邵志伟.测试性能估算的测试集重排序方法*[J].电子测量与仪器学报,2021,35(11):54-60
测试性能估算的测试集重排序方法*
Test set reordering method for test performance estimation
  
DOI:
中文关键词:  故障模型  测试性能  泊松分布  测试集重排序
英文关键词:fault model  test performance  poisson distribution  test set reordering
基金项目:安徽省重点研究与开发计划项目(201904f06020037)、安徽省高校协同创新项目(GXXT 2019 030)资助
作者单位
詹文法 安庆师范大学计算机与信息学院安庆246133 
彭登辉 安庆师范大学计算机与信息学院安庆246133 
邵志伟 安庆师范大学计算机与信息学院安庆246133 
AuthorInstitution
Zhan Wenfa School of Computer and Information, Anqing Normal University,Anqing 246133, China 
Peng Denghui School of Computer and Information, Anqing Normal University,Anqing 246133, China 
Shao Zhiwei School of Computer and Information, Anqing Normal University,Anqing 246133, China 
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中文摘要:
      目前在集成电路测试中,测试时间长、测试效率低是影响测试成本的关键问题之一,针对此问题提出了一种基于测试性能估算的测试集重排序方法。首先针对不同的故障类型进行分类建模,然后对每种故障类型进行仿真,通过在每个逻辑门注入故障,统计测试向量命中故障门的面积之和来估算测试向量的测试性能,最后根据测试性能的优劣对测试集进行重新排序。实验表明,对于单固定故障使用排序后的测试集测试可以减少5329%的故障检测时间。该方法是通过对电路的逻辑结构进行分析和统计然后对测试集进行优化,对ISCAS 89标准电路进行试验,与其他测试集重排序对比,有着明显的优化。算法运行完全是基于软件的,不需要增加任何硬件开销,可以直接相容于传统的集成电路测试流程。
英文摘要:
      At present, long test time and low test efficiency are one of the key problems affecting test cost in IC testing. To solve this problem, a test set reordering method based on test performance estimation is proposed. Firstly, different fault types are classified and modeled, and then each fault type is simulated. The test performance of test patterns is estimated by injecting faults into each logic gate and counting the total area of test patterns hitting the fault gate. Finally, the test sets are reordered according to the test performance. Experiments show that the sequenced test set test can reduce the fault detection time by 5329% for single stuck at fault. This method is to analyze and count the logic structure of the circuit and then optimize the test set, test the ISCAS 89 standard circuit, and compare it with other test sets to reorder it, which has obvious optimization. The algorithm operation is completely software based, without any additional hardware overhead, and can be directly compatible with the traditional integrated circuit test process.
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