| 庞高远,孟 煦,郭围围,尹勇生,邓红辉,陈红梅.新型两步式高精度 TDC 的设计[J].电子测量与仪器学报,2021,35(7):115-122 |
| 新型两步式高精度 TDC 的设计 |
| Design of a novel high precision TDC with two-step quantization |
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| DOI： |
| 中文关键词: 时间数字转换器 两步式 分辨率 测量范围 余量求取 |
| 英文关键词:time-to-digital converter two-step resolution measurement range residue generation |
| 基金项目:国家自然科学基金（61704043）、模拟集成电路重点实验室基金（6142802190506）项目资助 |
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| Author | Institution |
| Pang Gaoyuan | 1. Institute of VLSI Design, Hefei University of Technology |
| Meng Xu | 1. Institute of VLSI Design, Hefei University of Technology, Hefei,2. IC Design Web-Cooperation Research Center of MOE |
| Guo Weiwei | 1. Institute of VLSI Design, Hefei University of Technology |
| Yin Yongsheng | 1. Institute of VLSI Design, Hefei University of Technology, Hefei,2. IC Design Web-Cooperation Research Center of MOE |
| Deng Honghui | 1. Institute of VLSI Design, Hefei University of Technology, Hefei,2. IC Design Web-Cooperation Research Center of MOE |
| Chen Hongmei | 1. Institute of VLSI Design, Hefei University of Technology, Hefei,2. IC Design Web-Cooperation Research Center of MOE |
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| 中文摘要: |
| 时间数字转换器(TDC)是一种常用的时间间隔测量电路,广泛用于飞行时间(ToF)测量,频率测量等领域。 针对传统
TDC 分辨率与测量范围相互制约的问题,基于 SMIC 55 nm CMOS 工艺提出了一种兼顾分辨率与测量范围的两步式 TDC 结构。
该 TDC 第 1 级使用环形结构进行粗量化,以扩大测量范围;第 2 级利用延迟锁相环(DLL)结构精确控制压控延迟单元的延迟,
以产生代表分辨率的延迟差,进而实现细量化,提高了分辨率。 其中,设计了一种简便的时间余量求取算法,将第 1 级的粗量化
误差准确传递到第 2 级。 同时特别设计了第一级延迟单元的结构,以消除传统环形 TDC 中多路选择器(MUX)在信号循环过程
中造成的延迟失配。 仿真结果表明,该 TDC 的分辨率为 4. 8 ps,测量范围达到 1. 26 μs,微分非线性(DNL)小于 0. 6 LSB,积分
非线性(INL)小于 1. 8 LSB。 |
| 英文摘要: |
| Time-to-digital converter (TDC) is a time interval measurement circuit, widely used in time-of-flight (ToF) measurement,
frequency measurement and other fields. Aiming at the problem that traditional TDC was constrained by the mutual restriction of
resolution and measurement range, a novel TDC with two-step quantization that gave consideration to both resolution and measurement
range was designed in SMIC 55 nm CMOS process. The first stage used ring structure for coarse quantization, which improved the
measurement range. The second stage used a delay locked loop (DLL) to generate the control voltage that voltage-controlled delay cells
needed and improved the resolution by scaling the load capacitors of the delay cells. This paper proposed a simple algorithm of time
residue generation that transmitted the time interval cannot be quantified in first stage to second stage. The delay cell structure in first
stage was designed in order to eliminate the delay mismatch that multiplexer caused when signal circling. The simulation results showed
that the proposed TDC could realize the resolution of 4. 8 ps, the measurement range of 1. 26 μs. The measured maximum differential
non-linearity (DNL) is 0. 6 LSB. The measured maximum integral non-linearity (INL) is 1. 8 LSB. |
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