| 石 硕,王瑞雪,李 慧,韩昌彩.LDPC 码的多路并行编码器实现[J].电子测量与仪器学报,2021,35(7):83-89 |
| LDPC 码的多路并行编码器实现 |
| Implementation of multi-channel parallel encoder for LDPC codes |
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| DOI： |
| 中文关键词: 低密度奇偶校验码 编码器 多路并行 现场可编程门阵列 |
| 英文关键词:low-density parity-check(LDPC) codes encoder multi-channel parallel field programmable gate array(FPGA) |
| 基金项目:国家自然科学基金（61671324）项目资助 |
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| 摘要点击次数: 208 |
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| 中文摘要: |
| 针对空间数据系统咨询委员会(CCSDS)标准下低密度奇偶校验(LDPC)码编码器低硬件实现复杂度的应用需求,提出
一种适用于不同码长、码率 LDPC 码的多路并行编码器实现架构。 该架构通过重复利用编码器中的存储单元,将矩阵信息共享
到所有并行的运算单元中从而提高资源利用率。 进一步,在现场可编程门阵列(FPGA)平台上验证并测试码率分别为 1 / 2、2 / 3
及 4 / 5 的单路和多路编码器,测试结果表明采用多路并行架构的编码器吞吐量比单路编码器有明显的提高且均达到 1 Gbps 以
上;与达到基本相同吞吐量的单路多组编码器相比,其查找表资源分别减少 40%、44%和 46%。 该架构充分利用 FPGA 的存储
资源进而有效降低硬件实现复杂度。 |
| 英文摘要: |
| For the low implementation complexity requirement of the low-density parity-check ( LDPC) encoders in consultative
committee for space data systems (CCSDS) standard, an implementation architecture of multi-channel parallel encoder is proposed for
LDPC codes with different code lengths and code rates. The matrix information can be shared among all parallel computing units to
improve resource utilization by repeatedly utilizing the storage unit in the encoder. Furthermore, the single-channel and multi-channel
encoders with code rates of 1 / 2, 2 / 3 and 4 / 5 are verified and tested on the field programmable gate array (FPGA) hardware platform.
The test results show that the throughput of the encoders adopting the multi-channel parallel coding scheme is higher than that of the
single-channel encoders and achieves more than 1Gbps. The resources of the look-up table for the multi-channel encoders are reduced by
40%, 44% and 46%, respectively, compared with the single-channel encoders with multiple groups that achieves approximately the
same throughput. By making full use of the storage resources in FPGA, this architecture can reduce the complexity of hardware
implementation effectively. |
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