电子测量与仪器学报

佐磊,徐相相,陈昊,姜学义,朱良帅.基于改进最小二乘支持向量机的 FPGA 焊点失效故障评估方法研究[J].电子测量与仪器学报,2021,35(7):74-82

基于改进最小二乘支持向量机的 FPGA 焊点失效故障评估方法研究

Research on FPGA solder joint failure evaluation method based onimproved least square support vector machine

DOI：

中文关键词: FPGA 最小二乘支持向量机遗传算法焊接点失效 SJ BIST 测试

英文关键词:FPGA least squares support vector machine genetic algorithm solder joint failure SJ BIST test

基金项目:装备预先研究重点项目(41402040301)、国家重点研发计划(20l6YFF0102200)、国家自然科学基金重点项目(51637004)、国家自然科学基金(51777050)项目资助

作者	单位
佐磊	1. 合肥工业大学电气与自动化工程学院，2. 合肥工业大学可再生能源接入电网技术国家地方联合工程实验室
徐相相	1. 合肥工业大学电气与自动化工程学院
陈昊	1. 合肥工业大学电气与自动化工程学院
姜学义	1. 合肥工业大学电气与自动化工程学院
朱良帅	1. 合肥工业大学电气与自动化工程学院

Author	Institution
Zuo Lei	1. School of Electrical and Automation Engineering, Hefei University of Technology，2. National and Local Joint Engineering Laboratory of Renewable Energy Grid Technology, Hefei University of Technology
Xu Xiangxiang	1. School of Electrical and Automation Engineering, Hefei University of Technology
Chen Hao	1. School of Electrical and Automation Engineering, Hefei University of Technology
Jiang Xueyi	1. School of Electrical and Automation Engineering, Hefei University of Technology
Zhu Liangshuai	1. School of Electrical and Automation Engineering, Hefei University of Technology

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中文摘要:

针对现有现场可编程逻辑门阵列(FPGA)焊接点失效故障评估方法存在的无法提供准确的信息、样本数据少、时效性不高等问题,提出结合遗传算法(GA) 改进最小二乘支持向量机(GA-LS-SVM) 的 FPGA 焊接点失效故障评估方法。建立 SJ BIST 测试模型,选择合适的外接小电容,通过改变不同工作频率下可变电阻的大小模拟焊点阻值,获得基于小电容电压变化的故障数据,建立电容低电平的持续时间、电容测试工作频率和焊接点电阻值的三维数据图;最后利用遗传算法优化的最小二乘支持向量机对所得到的数据进行状态评估,由三维数据图可知,健康的 FPGA 焊接点与断裂的 FPGA 焊接点在低电平的持续时间具有明显差异。仿真实验结果表明,所提出的 GA-LS-SVM 方法焊接点健康状态等级分类的总准确率达到 97. 2%,相较于 BP 神经网络、标准 SVM 及 LS-SVM 方法分别提高了 17. 9%、13%及 7. 2%。

英文摘要:

Aiming at the problems in the current FPGA welding point failure assessment methods, such as the inability to provide accurate information, lack of sample data and low timeliness, combined with genetic algorithm (GA), an improved FPGA welding point failure assessment method based on the least square support vector machine (GA-LS-SVM) was proposed. Establish the SJ BIST test model, select the appropriate small external capacitor, simulate the welding spot resistance value by changing the variable resistor size at different operating frequencies, obtain the fault data based on the voltage change of small capacitor, and establish the three-dimensional data graph of the duration of capacitor low level, capacitor test working frequency and welding point resistance value; Finally using genetic algorithm to optimize the least squares support vector machine (SVM) to state evaluation of the obtained data, according to the three-dimensional data graph, there is a significant difference in the duration of low-level between healthy FPGA solder joints and broken FPGA solder joints. The simulation results show that the proposed GA-LA-SVM method has an overall accuracy rate of 97. 2%, which is 17. 9%, 13% and 7. 2% higher than BPNN, standard SVM and LS-SVM methods.

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