电子测量与仪器学报

肖瑞,陈红梅,王舰,谢熙明,王兰雨,尹勇生.基于参考通道随机化的 TIADC 校准算法[J].电子测量与仪器学报,2021,35(6):147-153

基于参考通道随机化的 TIADC 校准算法

A Ref. ADC-based calibration for time interleaved ADCsusing random sampling sequence

DOI：

英文关键词:time interleaved ADC kickback randomization reference ADC

基金项目:模拟集成电路重点实验室（6142802190506）项目资助

作者	单位
肖瑞	1. 合肥工业大学微电子设计研究所
陈红梅	1. 合肥工业大学微电子设计研究所,2. 教育部 IC 设计网上合作研究中心
王舰	1. 合肥工业大学微电子设计研究所
谢熙明	1. 合肥工业大学微电子设计研究所
王兰雨	1. 合肥工业大学微电子设计研究所
尹勇生	1. 合肥工业大学微电子设计研究所,2. 教育部 IC 设计网上合作研究中心

Author	Institution
Xiao Rui	1. Institute of VLSI Design, Hefei University of Technology
Chen Hongmei	1. Institute of VLSI Design, Hefei University of Technology,2. IC Design Web-Cooperation Research Center of MOE
Wang Jian	1. Institute of VLSI Design, Hefei University of Technology
Xie Ximing	1. Institute of VLSI Design, Hefei University of Technology
Wang Lanyu	1. Institute of VLSI Design, Hefei University of Technology
Yin Yongsheng	1. Institute of VLSI Design, Hefei University of Technology,2. IC Design Web-Cooperation Research Center of MOE

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中文摘要:

提出了一种针对时间交织模数转换器( time interleaved ADC,TI-ADC)通道间失配误差的基于参考通道的后台校准算法。该算法利用参考通道与同采样时刻 TI-ADC 子通道 ADC 输出差值估计待校准子 ADC 的失配误差,然后从系统输出中减之实现自适应误差补偿;为了克服当 TI-ADC 系统前端不存在单独输入缓冲器时,参考 ADC 通过输入网络耦合对 TI-ADC 产生干扰问题,进一步加入随机化技术,减少残余失配误差产生毛刺;该校准系统可以实现 3 种主要失配误差的同时有效校准,对输入信号带宽没有限制。应用于 12 位 1 GS / s TI-ADC 系统,当输入信号频率为 470 MHz 时,FPGA 验证结果表明,校准后无杂散动态范围(SFDR)提升了 44. 14 dB,达到 76. 16 dB。

英文摘要:

A background calibration algorithm based on ref. ADC is proposed for the mismatch in time interleaved ADC (TIADC). The difference between the output of the ref. ADC and sub-ADC at the same sampling time was used to estimate the mismatch, then subtracts the mismatch from the system output to realize adaptive calibration. Furthermore, randomization technology is adopted to solve the problem of the interference between the ref. ADC and TI-ADC, coupled through the input network when there is no separate input buffer at the front end of TI-ADC system by reducing residual interleaving spurs. The proposed algorithm can achieve effective calibration of the three main mismatch errors at the same time, and there is no limitation on the input signal bandwidth. Applied to a 12-bit 1 GS / s TIADC, when the input signal frequency is 470 MHz, FPGA verification results show that after calibration, the spurious-free dynamic range (SFDR) increase by 44. 14 dB to 76. 16 dB.

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